Desarrollo e implementación de la interface SBA para un núcleo pWM de 16 canales independientes programables

Abstract

iP cores (intellectual Property cores) are for hardware design what libraries are for computer programming. They are typically used in the style and form of a discrete integrated circuit, where the “circuit board” is a larger design in asic or FPGa. a core intellectual property often takes the form of a software program written in hDl such as verilog, vhDl or systemc. ideally, an iP-core must be fully portable, meaning that it can be easily adapted to any technology from other suppliers or different design methods. receivers/transmitters universal asynchronous (uart), central Processing units (cPu), ethernet controllers, interfaces Pci are examples of iP-cores. This paper presents the adaptation of a 16-channel PWm iPcore to a separate brick structure similar to soc (system on chip). We did not implement a microprocessor as master of the system, instead a complex state machine runs a bus in order to save resources in the FPGa. This complex state machine that acts as the controller of the system is within a provision which is called sba (single bus architecture), which is just a simplification of the signals and rules establishing the Wishbone specification. The system thus allows the configuration of 16 independent PWm digital outputs in low ripple mode. While the example presented in this work shows a single PWm iPcore instantiated this is not a limit. The implemented PWm core does not use specific or special resources of the FPGa, which allows that the number of instantiated blocks can grow as much as configurable generic blocks in the FPGa become available. That is, for each instantiated core there will be 16 independent PWm channels that will have specific preset positions within the address map of the sba.